Patent AT-E400845-T1: [Translated] COMPRESSING TEST RESPONSES USING A COMPACTOR

A method for testing an integrated circuit, comprising: ncapturing multiple test values in scan chains of a circuit-under-test, the test values being associated with a circuit response to a test pattern; nclocking the test values out of the scan chains and into a compactor; nproducing sets of two or more output values in the compactor, each set comprising all values produced in the compactor at least partially determined by a respective test value; and noutputting at least one of the sets from the compactor over at least two clock cycles and before all of the test values captured in the scan chain and associated with the circuit response to the test pattern have been clocked into the compactor.